![]() ![]() ![]() They are great compute devices and are especially useful for applications that lend themselves to parallel computation. FPGAs can be reconfigured to perform different functions by loading a new bit stream on to the device. Traditional FPGAs are configurable hardware devices. The answer lies in the fact that, although processors are continually offering better and better performance, they still lag far behind the performance-size-power ratio offered by hardware accelerators. One may ask the question as to why do we need the hardware accelerators at all. For example, if an SoC has a hardware block that supports a particular traffic management functionality (e.g., queuing, scheduling) or only supports a certain security algorithm, then any additional traffic management functions or security algorithms would have to be supported by the programmable portion of the SoC (i.e., the processor cores and GPUs). That is, customers can change the software portion of the application, but the hardware accelerators only perform the functions for which they were originally designed. These devices offer software flexibility via their processor cores and GPUs, but no flexibility when it comes to their hardware accelerators. SoCs generally target multiple markets and segments, and are not as narrowly defined as their ASIC/ASSP cousins. Some SoCs may contain fewer hardware blocks, while others may have more depending on the target application and market segment. ![]() These IP blocks generally consist of one or more processor cores (e.g., ARM, x86, PPC), GPUs, DSPs hardware accelerators such as a security/crypto engine and a deep packet inspection engine and communication interfaces (e.g., Ethernet, PCIe, RIO, SATA). Since ASICs/ASSPs are built to perform very specific functions, from an ROI (return on investment) perspective, they make sense only when the volumes are large as so to be able to recoup their substantial development costs.Īs their name suggests, SoC (System-on-Chip) devices comprise multiple IP blocks that are implemented on a single silicon die. As such, ASICs/ASSPs are developed for applications or functions that have matured or are standardized with no requirement for change in the future. However, ASICs/ASSPs do not offer any flexibility that is, once the device has been fabricated, it can only perform the specific function for which it was designed and nothing else. They offer the smallest die size and lowest power consumption, and they may have the best performance-to-power ratio. It is evident from this table that each device category has its own strengths and weaknesses.ĪSICs/ASSPs, SoCs & FPAGs: A brief descriptionĪSICs/ASSPs are built to perform very specific functions efficiently, and - as such - are optimized in terms of performance, power, and cost. High-level comparison of devices (Source: Dr. ![]()
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